library ieee; use ieee.std_logic_1164.all; entity combination3 is port(a,b,c:in std_logic; co,so:out std_logic); end combination3; architecture a of combination3 is begin so<=a xor b xor c; co<=((a xor b)and c)or(a and b); end architecture;
library ieee; use ieee.std_logic_1164.all; entity combination4 is port(G1,G2a,G2b:in std_logic; A:in std_logic_vector(2 downto 0); Y:out std_logic_vector(7 downto 0)); end entity combination4; architecture a of combination4 is begin process(A,G1,G2a,G2b) begin if(G1='1' and G2a='1' and G2b='1')then case A is when "000"=>Y<="00000001"; when "001"=>Y<="00000010"; when "010"=>Y<="00000100"; when "011"=>Y<="00001000"; when "100"=>Y<="00010000"; when "101"=>Y<="00100000"; when "110"=>Y<="01000000"; when "111"=>Y<="10000000"; end case; else y<="00000000"; end if; end process; end architecture;
四、 仿真验证与实验结果
从波形图可以看出输出Y和输入的三位二进制数一一对应,功能实现。
实验五表决器
一、实验内容
用 VHDL 语言设计实现一个 4 人表决器,多数人赞成决议表示通过,否则决议不通过。
使用波形图仿真验证其功能。
二、设计过程
得Y=A1A2A3+A2A3A4+A1A2A4+A1A3A4+A1A2A3A4
三、源代码
1 2 3 4 5 6 7 8 9 10
library ieee; use ieee.std_logic_1164.all; entity combination5 is port(A:in std_logic_vector(3 downto 0); Y:out std_logic); end combination5; architecture a of combination5 is begin Y<=(A(0) and A(1) and A(2)) or (A(0) and A(1) and A(3)) or (A(0) and A(3) and A(2)) or (A(3) and A(1) and A(2)) or (A(0) and A(1) and A(2) and A(3)); end architecture;